- 您现在的位置：买卖IC网 > Sheet目录1203 > COREPCIF-RM (Microsemi SoC)IP MODULE COREPCIF
Table 5-3 · Dataflow Interface Signals (Continued)
Name
Type
Width
Description
Memory address bus, where N is defined by the parameter MADDR_WIDTH
MEM_ADD
Output
N
bits of the PCI address bus. These address lines can be ignored for memory transfers but
may be used to verify the legality of I/O byte accesses.
MEM_DATA_IN
MEM_DATA_OUT
Input
Output
32/64
32/64
Data input, used for normal Target and Master data transfers as well as backend access to
the DMA control registers
Data output, used for normal Target and Master data transfers as well as backend access
to the DMA control registers
Active high data enable for the lower 32 bits of MEM_DATA_OUT. This is intended as
MEM_DATA_OE
Output
1
an output enable if MEM_DATA_IN and MEM_DATA_OUT are connected to
bidirectional I/O pads to create a bidirectional MEM_DATA bus.
Active high data enable for the upper 32 bits of MEM_DATA_OUT. This is intended as
MEM_DATA_OE64
Output
1
an output enable if MEM_DATA_IN and MEM_DATA_OUT are connected to
bidirectional pads to create a bidirectional MEM_DATA bus.
BYTE_VALN
Output
1
Active low strobe indicating that the BYTE_ENN outputs are valid.
Active low byte enables. To achieve high throughput, CorePCIF normally reads all four
bytes of data independently of the byte enable requests from the PCI bus. If the backend
logic is required to support byte read operations, the backend should wait until
BYTE_ENN
Output
4/8
BYTE_VALN is active (LOW) and then use this bus as read byte enables. Using this
transfer mode will significantly slow throughput. These outputs can also be used to verify
the legality of an I/O byte access before asserting WR_BE_RDY by comparing with the
lowest two bits of MEM_ADDR. If an illegal I/O access is detected, the ERROR input
can be asserted to cause a Target abort.
When LOW, this signal indicates that the core will sample data on the rising clock edge
while RD_STB_OUT and RD_STB_IN are active. When HIGH, this signal indicates
RD_SYNC
Input
1
that the core will sample data on the clock cycle after RD_STB_OUT and RD_STB_IN
are active. This should be set HIGH when synchronous memories are connected to the
backend interface.
Only has an effect when the FIFO recovery logic is enabled. If active (HIGH) when
RD_FLUSH
Input
6
DP_START occurs, the internal FIFO will be flushed. RD_FLUSH[0] is used to flush
the internal FIFO on BAR 0, RD_FLUSH[1] flushes the BAR 1 FIFO, etc. When the
FIFOs are flushed, any data that was stored in the internal FIFO will be lost.
Only used when the FIFO recovery logic is enabled and ENABLE_FIFOSTAT = 1.
Active low input indicating that the external FIFO connected to the core is empty. The
FIFO_EMPTYN
Input
6
any of the control logic in the core. It is only connected to the FIFO status register.)
46
v4.0
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
COREU1LL-AR
IP MODULE COREU1LL
COREU1PHY-AR
IP MODULE COREU1PHY
CORR-8BIT-XM-UT2
SITE LICENSE IP CORRELATOR XP
CP2-GSA-L
CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1
CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4
CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F
COMPACT PCI - MISC
CP2105EK
KIT EVAL FOR CP2105
相关代理商/技术参数
COREPCIF-RMFL
功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
COREPCIF-UR
功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
COREPCI-SN
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-SR
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-UR
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-XX
制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPRO LEDBULB 10.5-60W B
制造商:Philips Lumileds 功能描述:
COREPRO LEDBULB 10.5-60W E
制造商:Philips Lumileds 功能描述: